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doi = "10.7907/5xs37-cnf69" } @other{https://resolver.caltech.edu/CaltechAUTHORS:20120420-151015498, title = "Ray tracing parametric patches", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechAUTHORS:20120420-151015498", id = "record", doi = "10.7907/gsy5a-w9850" } @other{https://resolver.caltech.edu/CaltechCSTR:1982.5047-tr-82, title = "The torus: an exercise in constructing a processing surface", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1982.5047-tr-82", id = "record", doi = "10.7907/cazcq-6fz54" } @other{https://resolver.caltech.edu/CaltechAUTHORS:20120420-105611583, title = "VLSI algorithms for Doolittle's, Crout's, and Cholesky's methods", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechAUTHORS:20120420-105611583", id = "record", doi = "10.7907/4aq2m-bnw32" } @article{https://resolver.caltech.edu/CaltechCSTR:1982.5046-tr-82, title = "An Axiomatic Definition of Synchronization Primitives", journal = "Acta Informatica", publisher = "Springer-Verlag", url = "https://resolver.caltech.edu/CaltechCSTR:1982.5046-tr-82", id = "record", issn = "0001-5903", doi = "10.1007/BF00261260", volume = "16", number = "2" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4332-tr-81, title = "RLAP version 1.0 a chip assembly tool", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4332-tr-81", id = "record", doi = "10.7907/cpybe-b1d47" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4029-tr-81, title = "Structure, placement and modelling", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4029-tr-81", id = "record", doi = "10.7907/kq6fj-72673" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4320-tr-81, title = "A Hierarchical Design Rule Checker", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4320-tr-81", id = "record", doi = "10.7907/8jz33-x1385" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4336-tr-81, title = "A Structured Design Methodology \& Assoicated Software Tools", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4336-tr-81", id = "record", doi = "10.7907/n015c-49w50" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4654-tr-81, title = "A Versatile Ethernet Interface", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4654-tr-81", id = "record", doi = "10.7907/990sf-1kv28" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4281-tr-81, title = "Combining Graphics and a Layout Language in a Single Interactive System", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4281-tr-81", id = "record", doi = "10.7907/ptds4-39139" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4527-tr-81, title = "Communicative Databases", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4527-tr-81", id = "record", doi = "10.7907/p23xv-bcw17" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4168-tr-81, title = "Computational Arrays for the Discrete Fourier Transform", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4168-tr-81", id = "record", doi = "10.7907/n91j8-85m21" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4298-tr-81, title = "From Geometry to Logic", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4298-tr-81", id = "record", doi = "10.7907/xkcd6-vfg70" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4521-tr-81, title = "Lambda Logic", publisher = "California Institute of Technology", url = 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Science Department and the Caltech Industrial Associates Office, and sponsored by Caltech Industrial Associates and the National Science Foundation", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechAUTHORS:20120502-113421018", id = "record", doi = "10.7907/svt7c-01869" } @other{https://resolver.caltech.edu/CaltechCSTR:1980.2686-tr-1980, title = "The Caltech Intermediate Form for LSI Layout Description", publisher = "California Institute of Technology", url = "https://resolver.caltech.edu/CaltechCSTR:1980.2686-tr-1980", id = "record", doi = "10.7907/jmrgc-2f168" }