@inbook{https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704, title = "Advanced research in VLSI : proceedings of the fourth MIT conference, April 7-9, 1986", chapter = "An Integer Based Hierarchical Representation for VLSI", year = "1986", url = "https://resolver.caltech.edu/CaltechAUTHORS:20150112-140550704", id = "record", isbn = "9780262121132" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797, title = "VLSI '83 : VLSI design of digital systems : proceedings of the IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration, Trondheim, Norway, 16-19 August 1983", chapter = "Pooh: A Uniform Representation For Circuit Level Designs", year = "1983", url = "https://resolver.caltech.edu/CaltechAUTHORS:20150310-155318797", id = "record", isbn = "0444867511" } @other{https://resolver.caltech.edu/CaltechCSTR:1982.5029-tr-82, title = "Pooh User's Manual", year = "1982", url = "https://resolver.caltech.edu/CaltechCSTR:1982.5029-tr-82", id = "record", doi = "10.7907/hd624-pmr46" } @other{https://resolver.caltech.edu/CaltechCSTR:1981.4320-tr-81, title = "A Hierarchical Design Rule Checker", year = "1981", url = "https://resolver.caltech.edu/CaltechCSTR:1981.4320-tr-81", id = "record", doi = "10.7907/8jz33-x1385" } @inbook{https://resolver.caltech.edu/CaltechAUTHORS:20170802-153857139, title = "17th Conference on Design Automation", chapter = "Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking", year = "1980", url = "https://resolver.caltech.edu/CaltechAUTHORS:20170802-153857139", id = "record", isbn = "0-89791-020-6", doi = "10.1109/DAC.1980.1585254" }